Field of the Invention
The present invention relates to multiprocessor integrated circuits, in general, and to synchronisation of multiple microprocessors implemented on an integrated circuit, in particular.
Description of Related Art
Multiple microprocessors implemented on integrated circuits typically communicate through shared memory using memory mapped registers or general purpose input/output devices (GPIO's) connected to system interrupt signals as a mechanism for synchronising with one another. FIG. 1 is a diagrammatic representation showing one example of a system 1 on a programmable integrated circuit. The system 1 includes a first processor PA, a second processor PB, a shared memory device SMC and a memory mapped register RD. The processors PA and PB may include any logical mechanism known to those skilled in the art for supporting an instruction set. In one example, the processors PA and PB may include a central processing unit (CPU) or a digital signal processing (DSP) core having arithmetic logic units (ALUs) and multiply accumulate blocks (MACs). The processors PA and PB are operable to transfer data with the shared memory SMC, and with the memory mapped register RD. As will be described in more detail below, the memory mapped register RD is operable to output interrupt requests IRQPA and IRQPB to the processors PA and PB respectively.
Multi-processor systems often use sophisticated memory management systems to support synchronisation (for example, cache coherency, or locked memory blocks). Some processors allow semaphores to be implemented using “atomic” test-and-set (exchange) instructions. Semaphores are well known in the art and are used to control access to shared resources, such as memory, in multi-processor environments.
“Atomic” instructions are basic instructions which allow a semaphore to be tested or set.
In prior art system, various ad-hoc schemes are implemented on an application-by-application basis in order to synchronise multiple processors. In one known scheme, illustrated in FIG. 1 of the accompanying drawings, information is transferred between processors PA and PB in a number of steps. For example, to transfer data from processor PA to processor PB, processor PA places some data in a shared memory SMC. Processor PA then writes a data value to a memory mapped register RD. The register RD is connected to an interrupt request port on processor PB. When the processors PA and PB are provided on a single integrated circuit, the register RD is also provided on that integrated circuit. When the processors PA and PB are not implemented on the same integrated circuit RD is provided by a general purpose input/output device, GPIO. The act of writing a data value to the register to RD causes an interrupt request (IRQ) to be passed to the processor PB. This interrupt request IRQ causes the processor PB to execute an interrupt service routine (ISR). The processor PB now reads the stored data out of the shared memory SMC.
The method described scheme can also be used in a reverse fashion so that the processor PB can send data and an interrupt request to processor PA. Such bidirectional communication allows a so-called “handshake” to be performed. That is, processor PA can generate an interrupt request communicating to PB the message “the data in SMC is ready”, processor PB then generates an interrupt request to processor PA communicating back to PA the message “I have finished with the data”. This communication between processors allows processes (or threads) running on respective processors to synchronise and communication with one another.
However, the scheme as described above relies on the integrated circuit hardware designer to construct a protocol for synchronising processes using interrupt requests (IRQs) and interrupt service routines (ISRs). If the application software is changed so that different communication patterns are required, new memory mapped registers (RD) and interrupt (IRQ) connections will have to be added and the hardware rebuilt. Such redesign and rebuild is clearly inefficient and costly.